// ==================================================================================
// FileName : Intro_Top.v
// Fucntion : Top level of a simple design.
//
// This module contains the top structure of the design, which
// is made up of three lower-level modules and one inverter gate.
// The structure is represented by module instances.
//
// What is JTAG? (useful in DFT)
//
// Joint Test Action Group (JTAG) is the common name for the IEEE 1149.1 Standard Test
// Access Port and Boundary-Scan Architecture. It was initially devised by electric
// engineers for testing printed circuit boards(PCB) using boundary scan and is still
// widely used for this application.
//
// Today, JTAG is also widely used for IC debug ports. In the embedded processor 
// market, essentailly all modern processors implement JTAG when they have enough pins
// Embedded system development relies on debuggers communicating with chips with JTAG
// to perform operations like single stepping and breakpointing.
// ----------------------------------------------------------------------------------
//
// Author   : QilinZhao
// Version  : v-1.0
// Date     : 2013-08-29
// E-mail   : forqilin@163.com
// Copyright: QiXin Studio
// =================================================================================
module Intro_Top ( output X, Y, Z, input A, B, C, D,   // function mode
                   output ScanOut,
                   input ScanMode, ScanIn, ScanClr, ScanClk  // JATG port : test mode
                 );
  wire ab, bc, q, qn;  // Wires for internal connectivity.
  
  assign #1 Z = ~qn; // Inverter by continuous assignment statement.
  
   AndOr InputCombo  (.X(ab), .Y(bc), .A(A), .B(B), .C(C));
      SR SRLatch     (.Q(q), .Qn(qn), .S(bc), .R(D));
  XorNor OutputCombo (.X(X), .Y(Y), .A(ab), .B(q), .C(qn));
  
endmodule // Intro_Top
